Semiconductor ICs include active devices formed on a semiconductor substrate, with an interconnect structure formed over the active devices. The interconnect structure typically includes from three to 15 printed circuit layers. Each printed circuit layer is formed of an intermetal dielectric (IMD) material having one or more trenches, which are filled with a conductive material, such as copper or aluminum, to form conductive lines. Each IMD layer also includes a plurality of conductive vias, which connect lines in adjacent layers.
The materials and layout of the IMD layers are selected to minimize size, propagation delays, and crosstalk between nearby lines. One technique for achieving these goals is the use of IMD materials with low dielectric constants. As designs are developed for advanced technology nodes (e.g., with a critical dimension of 65 nm, 45 nm or smaller), the use of materials having a dielectric constant (k) less than that of silicon dioxide is being considered, including low-k materials having a k value of less than 3.5 and extreme low-k (ELK) having a k value of less than 3.0. For example, two low-k materials that are being explored extensively for advanced technology ICs are “BLACK DIAMOND™” carbon doped silicon dioxide (k˜3.0), sold by Applied Materials, Inc., of Santa Clara, Calif., and “SiLK™” aromatic hydrocarbon thermosetting polymer (k˜2.7), sold by Dow Chemical Company of Midland, Mich. For lower dielectric constants, foundries have also considered use of porous dielectric materials, since the value of k for air is 1.0. Using porous dielectric materials, an average k value for the IMD layers can be reduced to about 2.0.
Unfortunately, ELK materials have mechanical properties that are less advantageous than those of SiO2. ELK materials tend to be brittle relative to SiO2. For example, although SiO2 has an elastic modulus of 78 Gpa, for “SiLK™” the modulus is only 2.7 Gpa. Also, although the coefficient of thermal expansion (CTE) of SiO2 is compatible with the IC substrate and the package substrate to which the IC will be mounted, many low-k and ELK materials have CTE values that differ substantially from that of the package substrate. As a result, during tests, de-lamination and cracking of the top IMD layers have been observed.